sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? high-speed access times of 10, 12, 15 and 20 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce\ and oe\ options ? ce\ power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 3.3v power supply 128k x 8 sram high-speed cmos sram with 3.3v revolutionary pinout pin assignment (top view) 32-pin, 400-mil plastic soj (dj) & ceramic soj (dcj) general description the asi as5lc1008 is a very high-speed, low power, 131,072-word by 8-bit cmos static ram in revolutionary pinout. the as5lc1008 is fabricated using high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce\ is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250w (typical) with cmos input levels. the as5lc1008 operates from a single 3.3v power supply and all inputs are ttl-compatible. options marking ? timing 10ns access -10 12ns access -12 15ns access -15 20ns access -20 ? package plastic soj (32-pin, 400-mil) dj no. 906 *ceramic soj (32-pin, 400-mil) dcj no. 501 ? operating temperature ranges -military (-55 o c to +125 o c) xt -industrial (-40 o c to +85 o c) it *consult factory, possible future offering for more products and information please visit our web site at www.austinsemiconductor.com pin functions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a0 a1 a2 a3 ce\ i/o 0 i/o 1 vcc gnd i/o 2 i/o 3 we\ a4 a5 a6 a7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a15 a14 a13 oe\ i/o 7 i/o 6 gnd vcc i/o 5 i/o 4 a12 a11 a10 a9 a8 pin description a0 - a16 address inputs ce\ chip enable input oe\ output enable input we\ write enable input i/o0 - i/o7 bidirectional ports v cc power gnd ground
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 absolute maximum ratings* terminal voltage with respect to gnd (v term )...........................................................................................-0.5v to v cc + 0.5v temperature under bias (t bias ).............................................................................................................................- 55c to +125c storage temperature (t stg ).............................................................................................................................. ......-65c to +150c power dissipation (p t ).............................................................................................................................. ..................................1.0w *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification i s not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. functional block diagram truth table mode we\ ce\ oe\ i/o operation v cc current not selected (power-down) x h x high-z i sb1 , i sb2 output disabled h l h high-z i cc1 , i cc2 read h l l d out i cc1 , i cc2 write l l x d in i cc1 , i cc2 a0 - a16 v cc gnd i/o0 - i/o7 ce\ oe\ we\ decoder 128k x 8 memory array i/o data circuit column i/o control circuit
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 electrical characteristics and recommended dc operating conditions (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 3.3v +0.3v) parameter symbol conditions min max units output high voltage v oh v cc = min., i oh = -4.0ma 2.4 --- v output low voltage v ol v cc = min., i ol = 8.0ma --- 0.4 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage 1 v il -0.3 0.8 v input leakage i li gnd < v in < v cc -5 5 a output leakage i lo gnd < v out < v cc ; outputs disabled -5 5 a note: 1. v il = -3.0v for pulse width less than 10ns. power supply characteristics 1 (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 3.3v +0.3v) note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. capacitance 1,2 parameter symbol conditions max unit input capacitance c in v in = 0v 6pf input/output capacitance c i/o v out = 0v 8pf note: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1mhz, v cc = 3.3v. parameter sym conditions min max min max min max min max unit v cc dynamic operatin g supply current i cc v cc = max, ce\ = v il , i out = 0 ma, f = max --- 160 --- 140 --- 130 --- 120 ma i sb v cc = max, v in = v ih or v il ce\ > v ih , f = max --- 45 --- 40 --- 35 --- 30 ma i sb1 v cc = max, v in = v ih or v il ce\ > v ih , f = 0 --- 30 --- 30 --- 30 --- 30 ma cmos standby current (cmos inputs) i sb2 v in > v cc - 0.2v, or v in < 0.2v, f = 0 --- 10 --- 10 --- 10 --- 10 ma -10 -12 -20 ttl standby current (ttl inputs) -15
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 read cycle switching characteristics 1 (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 3.3v +0.3v) notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and c1 output loading specified in figure 1. 2. tested with the c2 load in figure 1. transition is measured 500 mv from steady-state voltage. not 100% tested. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3ns input and output timing and reference levels 1.5v output load see figures 1 and 2 figure 1 figure 2 ac test loads parameter symbol min max min max min max min max unit read cycle time t rc 10 --- 12 --- 15 --- 20 --- ns address access time t aa --- 10 --- 12 --- 15 --- 20 ns output hold time t oha 2 --- 2 --- 2 --- 2 --- ns ce\ access time t ace --- 10 --- 12 --- 15 --- 20 ns oe\ access time t doe --- 5 --- 6 --- 7 --- 8 ns oe\ to low-z output t lzoe 2 0 --- 0 --- 0 --- 0 --- ns oe\ to high-z output t hzoe 2 05060708ns ce\ to low-z output t lzce 2 2 --- 2 --- 2 --- 2 --- ns ce\ to high-z output t hzce 2 05060708ns -10 -12 -20 -15
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 read cycle #1 1,2 read cycle #2 1,3 notes: 1. we\ is high for a read cycle. 2. the device is continuously selected. oe\, ce\ = v il . 3. address is valid prior to or coincident with ce\ low transitions.
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 write cycle switching characteristics 1,3 (-55 o c < t a < +125 o c or -40 o c to +85 o c; vcc = 3.3v +0.3v) write cycle #1 1,2 (ce\ controlled, oe\ = high or low) notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 200 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce\ low and we\ low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the sign al that terminates the write. -10 parameter symbol min max min max min max min max units write cycle time t wc 10 --- 12 --- 15 --- 20 --- ns ce\ to write end t sce 7 --- 8 --- 9 --- 10 --- ns address setup time to write end t aw 8 --- 9 --- 10 --- 12 --- ns address hold from write end t ha 0 --- 0 --- 0 --- 0 --- ns address setup time t sa 0 --- 0 --- 0 --- 0 --- ns we\ pulse width (oe\ high) t pwe1 1 7 --- 8 --- 9 --- 10 --- ns we\ pulse width (oe\ low) t pwe2 2 10 --- 12 --- 12 --- 15 --- ns data setup to write end t sd 5 --- 6 --- 7 --- 8 --- ns data hold to write end t hd 0 --- 0 --- 0 --- 0 --- ns we\ low to high-z output t hzwe 2 --- 5 --- 6 --- 7 --- 8 ns we\ high to low-z output t lzwe 2 2 --- 2 --- 2 --- 2 --- ns -20 -12 -15
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 notes: 1. the internal write time is defined by the overlap of ce\ low and we\ low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the sign al that terminates the write. 2. i/o will assume the high-z state if oe\ ? v ih . write cycle #3 (we\ controlled, oe\ = low during write cycle) write cycle #2 1 (we\ controlled, oe\ = high during write cycle)
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 asi case #906 (package designator dj) mechanical definition* * all measurements are in inches. min max a 0.128 0.148 a1 0.025 --- a2 0.082 --- b 0.015 0.020 b 0.026 0.032 c 0.007 0.013 d 0.820 0.830 e 0.435 0.445 e1 0.395 0.405 e2 e 0.370 bsc 0.050 bsc symbol asi specifications
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 *all measurements are in inches. asi case #501 (package designator dcj) possible future offering, contact factory mechanical definitions* a a2 e b d e d1 e1 e2 b1 min max a 0.132 0.144 a2 0.026 0.036 b1 0.030 0.040 b1 0.015 0.019 d 0.812 0.828 d1 0.740 0.760 e 0.405 0.415 e1 0.435 0.445 e2 0.360 0.380 e symbol asi specifications 0.050 bsc
sram sram sram sram sram as5lc1008 austin semiconductor, inc. as5lc1008 rev. 1.0 11/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = military temperature range -55 o c to +125 o c device number package type speed ns process as5lc1008 dj -10 /* as5lc1008 dj -12 /* as5lc1008 dj -15 /* as5lc1008 dj -20 /* device number package type speed ns process as5lc1008 dcj -10 /* as5lc1008 dcj -12 /* as5lc1008 dcj -15 /* as5lc1008 dcj -20 /* example: as5lc1008dj-12/xt example: as5lc1008dcj-10/it
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